As a size of a MOSFET has entered into a nano scale, adverse impacts such as short channel effect of the device and so on are becoming severe, and an off-state leakage current of the device is increasing continuously. At the same time, since a sub-threshold slope of a conventional MOSFET is limited by a thermoelectric potential and thus not decrease synchronously with a shrink of the device, a theoretical limitation of 60 mV/dec is existed. This has caused that a further increasing of leakage current with a drop of a power supply, thus increasing a power consumption of the device. A problem regarding to the power consumption has now become one of the most severe issues restricting scaling-down of the device. In a realm of ultra low voltage and low power consumption, a tunneling field effect transistor (TFET) has become something of a hot topic on the grounds of having a very low leakage current and an ultra steep sub-threshold slope.
Unlike the conventional MOSFET, the TFET has a source and a drain with doping types of opposite to each other, and a channel region and a body region which are both intrinsically doped. The TFET is turned on through by controlling a quantum band-to-band tunneling of a reverse biased P-I-N junction by a gate. The TFET can operate under a lower voltage and has a process compatible with a conventional CMOS process. Practically in a small size standard CMOS IC fabrication process, however, in order to suppress a short channel effect of the MOSFET to prevent a punchthrough, a doping concentration in the body region (a sub surface) of the MOSFET is high while a surface region is lightly doped. However, the concentrations in both of the regions are very high for the TFET. If the TFET is integrated completely based on the standard CMOS IC process, leakage current of the TFET would be increased and there would be an impact to turning-on characteristics of the TFET. In addition, since an obvious bipolar turning-on effect is existed in the TFET, applications of the TFET in integrated circuits are greatly limited. Although the bipolar effect of the TFET may be inhibited in a way of lowering the concentration of the drain to implement a complementary TFET, further photolithographic masks need to be added on a basis of the standard CMOS IC process, which increases process complexity and manufacturing cost.